Implementation of Fast, Power and Energy Efficient CMOS Flip-Flops in 45 Nm Regime

Abstract

This paper presents the design and simulation of three novel D-flip-flops in Cadence 45nm CMOS technology. They are Implicit Pulsed Dual-Edge Triggered D Flip-Flop (IPDFF), D-Flip-Flop with Asynchronous Reset (DFFAR), and 18-transistor Single-Phase Clocked (18-TSPC) D-Flip-Flop aimed at achieving the lowest power, delay and energy efficiency in modern digital Systems. The first flip-flop is an Implicit Pulsed Dual-Edge Triggered D-Flip-Flop using CMOS VLSI pass transistor logic and dual-edge triggering for efficient clocking with reduced transistor count and leakage current thus targeting low-power, low-energy portable applications. The second flip-flop is the D-Flip Flop with Asynchronous Reset (DFFAR) that addresses power aspects while ensuring complete data integrity reliability and immediate reset capabilities. The third design, a single-phase clocked flip-flop (18-TSPC) with 18 transistors realizes high speed, optimizes power consumption and stability for compact high-performance applications. Results show that IPDFF exhibits the lowest power consumption of 0.0308µW and the lowest energy 0.0029fJ, making it highly efficient for IoT devices, embedded systems, and battery-operated electronics. DFFAR despite its higher delay of 4157ps, has exceptional low power consumption of 0.176µW making it suitable for power-sensitive applications. 18-TSPC flipflop achieves the shortest propagation delay of 5.064ps but consumes higher power of 14.16µW, making it ideal for high-speed applications like real-time processing and high-frequency computing.