Optimal Design for High Performance Computing Systems Based on 5-Stage Pipeline 32-bit RISC-V Processor

Abstract

In an era where computational demands continually escalate, the quest for more efficient and powerful processors persists. Computer engineering and VLSI design industries are facing challenges with the trade-offs between the cost and performance of components in the implementation domain. Reduced Instruction Set Computer (RISC) architecture relies its focus mainly on scaling down the complexity and the number of instructions in the microprocessor. RISC-V is an Open-source Instruction set architecture (ISA) designed to be simple, modular, and customizable. The most important feature of RISC is that it supports load-store architecture. With this feature, an optimized 32-bit microprocessor has been designed with Verilog, simulated and synthesized in Xilinx Vivado. Verilog enables us to describe the behavior and structure of our processor at a register-transfer level. Overall, RISC-V's combination of simplicity, openness, and flexibility positions it as a promising ISA for a wide range of applications, from low-power IoT devices to high-performance computing systems.