Iterative Dadda Tree Architecture for High-Performance Booth and Wallace Multipliers

Abstract

The proposed work presents two hybrid multiplier architectures—Dadda-Wallace and Dadda-Booth—designed to address the increasing demand for fast, area-efficient, and low-power multiplication units in modern digital systems. The Dadda-Wallace hybrid combines the compact, hardware-efficient reduction strategy of the Dadda multiplier with the parallel, high-speed compression of the Wallace tree, achieving a balanced trade-off between area and delay. The Dadda-Booth hybrid integrates Booth encoding for signed number multiplication with the Dadda reduction tree, enabling efficient handling of signed operands while minimizing partial products and reducing overall computation time. Both architectures target scalability and adaptability across varying operand sizes, making them suitable for embedded systems, machine learning accelerators, and digital signal processing applications. Through comprehensive analysis and benchmarking, the proposed Booth-Dadda architecture achieves outstanding results, including a LUT utilization of just 0.10% (134/133,800), I/O utilization of 6.40% (32/500), a worst hold slack of 5.632 ns, total on-chip power consumption of only 0.12 W, and stable thermal characteristics at 25.2 °C with a margin of 74.8 °C. These hybrids demonstrate superior performance compared to traditional multipliers by effectively reducing critical path latency, minimizing gate count, and maintaining computational accuracy. This research fills the gap left by conventional multiplier architectures that often optimize only one or two metrics, presenting a holistic approach that meets modern computing demands with an optimal Power-Performance-Area (PPA) trade-off.