Low-Power DSP Architectures for Wireless Communication Using Vedic Mathematics

Abstract

In this research work, a Vedic mathematics-based computation technique has been used to explore low-power DSP architectures for wireless communication. Finally, Urdhva Tiryagbhyam, Nikhilam, and Paravartya algorithms are studied in this thesis and the results indicate that these algorithms use less energy, take less time to execute, less time taking and fast algorithm. Statistical modelling, clustering and machine learning-based prediction are performed for performance analysis. Results show that optimized DSP architectures offer a very significant improvement in signal processing efficiency, and thus, are very appropriate for input/output (IoT), 5G and embedded systems. Therefore, the study proposes the integration of Vedic-based DSP in high-performance low-power wireless communication solutions.