Power and Energy Efficient Techniques for Full Adder – Implementation, Comparison and Analysis in 45 Nm Technology

Abstract

The 1-bit full adder is a crucial digital component in arithmetic implementations, processors, and digital filters. Reducing its power consumption is essential for minimizing the overall power of digital systems. This paper presents an extensive study on various lowpower techniques for a 1-bit full adder, focusing on logic styles, hybrid digital styles, redundant components, and methods for reducing transistor count. Three techniques are explored: Gate-Diffused Input (GDI) for voltage swing reduction, redundant component-based multiplexers for power reduction and circuit simplicity, and hybrid module implementation combining different techniques. This work explores six proposed full adder (FA) designs: GDI1, GDI2, GDI3, GDI4, Mux based, Hybrid Full adders. The implementations are carried out using 45 nm process node using Cadence Virtuoso, with results analysed, tabulated, and compared. This study offers valuable insights into the effectiveness of different low-power techniques for 1-bit full adder design, enabling the development of energy-efficient digital systems. The 16T Hybrid FA design stands out as the most efficient in terms of power, delay, and Power Delay Product (PDP). MUX-based and GDI1, GDI2 implementations also show lowest power compared to traditional CMOS designs. Approximately 54.88% less power and 86.68% less delay is used by the Hybrid Full Adder than by the CMOS Full Adder.