Design and Optimization of Reversible Quaternary Scalable Multiplexers and De-multiplexers

Abstract

Minimizing information loss in digital systems is important because it helps in saving power. Quaternary reversible circuits, which use four levels of logic instead of the usual two, are becoming popular because they can be more energy-efficient. This paper introduces a new and scalable design for key circuits in computing, specifically 4 × 1 Multiplexers and 1 × 4 Demultiplexers, and also n x 1 multiplexers and 1 x n Demultiplexers using special gates designed for quaternary logic. This paper proposes, a general method for building larger versions of these circuits. Compared to existing designs, proposed circuits will be more efficient because they use fewer resources and produce less waste, which will improve the performance of processors in digital systems. In circuit analysis, multiplexers and demultiplexers are essential components of the Arithmetic Logic Unit (ALU). The performance of the processor is greatly impacted by their effective design. This work realized by using EDA tools and performance of proposed techniques is analyzed in terms of quantitative outcomes and calculating Power, Delay and Power Delay Product (PDP) in Nano meter technology.