Design of a High speed Low Low-Power Latched Comparator for Medical Implants

Abstract

The latched dynamic  comparator is a fundamental component in all ADC architectures. Thermal effects, kickback, and offset voltage influence it. The kickback noise of the latched comparator in medical implant ADCs can impact the resolution, precision, and settling period. The current study examines a latching comparator that aims to reduce kickback noise. This research presents a low-power latched comparator for medical implants functioning at 1 V. This investigation implements a comparator utilising the sampling switching approach. This method successfully minimises kick-back noise and clocking feed-through by minimising unwanted charge injections in the comparator. The comparator decreases power usage while maintaining noise levels. The comparator uses 45-nanometre CMOS technology. The proposed comparator demonstrates superior performance compared to leading comparators regarding kickback noise, power consumption, delay. The input voltage has an inverse effect on the comparator's delay. Simulations indicate that the comparator uses 31 nW at 1 V. The comparator consumes 70% less power compared with different systems. The suggested sample modification decreases kickback noise by a minimum of 18%.