Design and Analysis of High Speed Low Power 4T-2R finFET-Memristor based SRAM

Abstract

Power usage management has emerged as a significant challenge in the production process due to the continued miniaturisation of CMOS technology. All standards for developing designs of non-volatile storage are going to gain through the implementation of memristors. Memristive devices have been defined by non-volatility, significant switching frequency, minimal energy consumption, and small dimensions.  FinFETs may replace conventional transistors, significantly enhancing efficiency in space and power, hence improving the design. The development of a non-volatile SRAM unit using FinFET and Memristor is suggested and compared to conventional SRAMs. Compared to current CMOS 6T SRAM and finFET 6T SRAM, the proposed SRAM exhibits significantly reduced power consumption and demonstrates speed improvements of at least 87% and 54%, respectively. Furthermore, Monte Carlo calculations have been conducted for the described 6T-SRAM architecture to enhance comprehension of the device's robustness.