Evaluation of Hardware Trojans in the Adder circuits

Abstract

Exporting the design and fabrication of Integrated Circuits (ICs) presents a significant risk to our vital infrastructure since an attacker may exploit them by circumventing security measures by triggering a hardware Trojan. These malicious design changes implemented at an untrusted manufacturing site have the potential to leak nearly any confidential information from a protected system to an attacker. One of the most serious dangers to hardware security has been the hardware Trojan.  We present a summary of recent advances in Trojan detection approaches, grouped according to their relevance to various Trojan kinds. Adder has indeed been implemented effectively in integrated circuits like arithmetic circuits as well as arithmetic accelerators. However, recent research indicates that adder circuits contain security flaws as well. Nevertheless, there has been relatively little study of hardware Trojans within adder circuits. The Trojans are based on the attributes of adder circuits. The efficacy of hardware Trojans is often evaluated using adder circuit assessment methodologies. The performance characteristics of adder like power and delay are evaluated with and without hardware Trojans.